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BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/ D input to control the direction of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary sequence. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.
SN54/74LS168 SN54/74LS169
BCD DECADE/ MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY
* * * * * * *
Low Power Dissipation 100 mW Typical High-Speed Count Frequency 30 MHz Typical Fully Synchronous Operation Full Carry Lookahead for Easy Cascading Single Up / Down Control Input Positive Edge-Trigger Operation Input Clamp Diodes Limit High-Speed Termination Effects
J SUFFIX CERAMIC CASE 620-09
16 1
CONNECTION DIAGRAM DIP (TOP VIEW)
V CC 16 TC 15 Q 0 14 Q 1 13 Q 2 12 Q 3 11 CET 10 PE 9
16 1
N SUFFIX PLASTIC CASE 648-08
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 U/D 2 CP 3 P 0 4 P 1 5 P 2 6 P 3 7 CEP 8 GND
16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.
CEP CET CP PE U/D P0-P3 Q0-Q3 TC
Count Enable Parallel (Active LOW) Input Count Enable Trickle (Active LOW) Input Clock Pulse (Active positive going edge) Input Parallel Enable (Active LOW) Input Up-Down Count Control Input Parallel Data Inputs Flip-Flop Outputs Terminal Count (Active LOW) Output
0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.
LOGIC SYMBOL
9 3 4 5 6
PE 1 7 10 2 U/D CEP CET CP
P 0
P 1
P 2
P 3
TC
15
NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.
Q 0
Q 1
Q 2
Q 3
14
13
12
11
V = PIN 16 CC GND = PIN 8
FAST AND LS TTL DATA 5-302
SN54/74LS168 * SN54/74LS169
STATE DIAGRAMS SN54/ 74LS168 UP / DOWN DECADE COUNTER
0 1 2 3 4 0
SN54 / 74LS169
1
2
3
4
15
5
15
5
14
6
Count Up Count Down
14
6
13
7
13
7
12
11
10
9
8
12
11
10
9
8
SN54 / 74LS168 UP: TC = Q0 Q3 (U / D) DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
SN54 / 74LS169 UP: TC = Q0 Q1 Q2 Q3 (U / D) DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
LOGIC DIAGRAMS SN54 / 74LS168
P 0 PE P 1 P 2 P 3
CEP CET U/D
TC
CP CP D
Q 0
Q 1
Q 2
Q 3
FAST AND LS TTL DATA 5-303
SN54/74LS168 * SN54/74LS169
LOGIC DIAGRAMS (continued) SN54 / 74LS169
P 0 PE P 1 P 2 P 3
CEP CET U/D
TC
CP CP D
Q 0
Q 1
Q 2
Q 3
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA
FAST AND LS TTL DATA 5-304
SN54/74LS168 * SN54/74LS169
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs CET Input Other Input CET Input IIL IOS ICC Input LOW Current Other Input CET Input Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 34 V A 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V
IIH
mA
VCC = MAX, VIN = 7.0 V
mA mA mA
VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION The SN54/74LS168 and SN54/74LS169 use edgetriggered D-type flip-flops that have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0 - P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH. The U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the COUNT DOWN mode or reaches 15 (9 for the SN54/74LS168) in the COUNT UP mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. The TC output of the SN54/74LS168 decade counter can also be LOW in the illegal states 11, 13 and 15, which can occur when power is turned on or via parallel loading. If illegal state occurs, the SN54/74LS168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended.
MODE SELECT TABLE
PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn Qn) Count Up (increment) Count Down (decrement) No Change (Hold) No Change (Hold)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
FAST AND LS TTL DATA 5-305
SN54/74LS168 * SN54/74LS169
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to TC Propagation Delay, Clock to any Q Propagation Delay, CET to TC Propagation Delay, U / D to TC Min 25 Typ 32 23 23 13 15 15 15 17 19 35 35 20 23 20 20 25 29 Max Unit MHz ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions
AC SETUP REQUIREMENTS (TA = 25C)
Limits Symbol tW ts ts ts th Parameter Clock Pulse Width Setup Time, Data or Enable Setup Time PE Setup Time U/D Hold Time Any Input Min 25 20 25 30 0 Typ Max Unit ns ns ns ns ns Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA 5-306
SN54/74LS168 * SN54/74LS169
AC WAVEFORMS
1/fmax tW CP 1.3 V 1.3 V 1.3 V CET 1.3 V tPLH 1.3 V 1.3 V tPHL 1.3 V
tPHL Q OR TC 1.3 V
tPLH 1.3 V
TC
Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width
Figure 2. Count Enable Trickle Input To Terminal Count Output Delays
CP ts(H)
1.3 V
1.3 V
th(H) = 0
ts(L)
th(L) = 0
CP
1.3 V tPLH 1.3 V
1.3 V
1.3 V tPHL 1.3 V
P0
* P1 * P2 * P3
1.3 V
1.3 V
1.3 V
1.3 V
TC
Q0
* Q1 * Q2 * Q3
Figure 3. Clock to Terminal Delays
Figure 4. Setup Time (ts) and Hold (th) for Parallel Data Inputs
CP ts(L)
1.3 V
1.3 V
th(L) = 0 SR OR PE 1.3 V 1.3 V
ts(H)
th(H) = 0 1.3 V U/D
1.3 V
1.3 V
1.3 V
tPLH CP ts(H) 1.3 V 1.3 V 1.3 V TC 1.3 V
tPHL 1.3 V
th(H) = 0 1.3 V
ts(L)
th(L) = 0 1.3 V
CEP 1.3 V
1.3 V
Figure 6. Up-Down Input to Terminal Count Output Delays
ts(L) th(L) = 0
ts(H)
th(H) = 0 1.3 V
CET 1.3 V
1.3 V
1.3 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 5. Setup Time and Hold Time for Count Enable and Parallel Enable Inputs, and Up-Down Control Inputs
FAST AND LS TTL DATA 5-307
-A-
Case 751B-03 D Suffix 16-Pin Plastic SO-16
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03.
16
9
-B1 8
P
8 PL
0.25 (0.010)
M
B
M
R X 45 G -TD 16 PL
0.25 (0.010)
M
C
SEATING PLANE
K
T B
S
M
F
J
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX
9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25
INCHES MIN MAX
0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049
1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50
0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019
Case 648-08 N Suffix 16-Pin Plastic -A16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08.
B
1 8
F S
C -TK
SEATING PLANE
L
H G D 16 PL
0.25 (0.010)
M
J
M
T
A
M
DIM A B C D F G H J K L M S
MILLIMETERS MIN MAX
18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77
INCHES MIN MAX
0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070
2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.51 0.38 3.30 7.74 10 1.01
0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.020 0.015 0.130 0.305 10 0.040
-A16 9
Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
-B1 8
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
C
L
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09.
-TSEATING PLANE
K E F D 16 PL
0.25 (0.010)
M
N G
T A
S
M J 16 PL
0.25 (0.010)
M
T
B
S
DIM A B C D E F G J K L M N
MILLIMETERS MIN MAX
19.05 6.10 19.55 7.36 4.19 0.39 0.53
INCHES MIN MAX
0.750 0.240 0.770 0.290 0.165 0.015 0.021
1.27 BSC 1.40 1.77
0.050 BSC 0.055 0.070
2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.39 15 0.88
0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 0.015 15 0.035
FAST AND LS TTL DATA 5-308
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FAST AND LS TTL DATA 5-309

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